(1) Field of the Invention PA1 (2) Prior Art
The present invention relates to the field of computation and logic units. Specifically, the present invention relates to the field of addressing schemes for an arithmetic integer pipeline ("arithmetic pipeline").
Arithmetic and logic computations are typically performed within a digital computer by specialized components designed in hardware. One hardware unit developed for addition and subtraction as well as other logical functions is called an arithmetic integer pipeline ("unit") which may be implemented for executing arithmetic instructions, sometimes called ALU instructions. Another hardware unit of a digital computer designed for mathematical functions is a multiplier. Common to all prior art hardware components utilized for arithmetic and logic computations is that they address two, three or four operands (which are addresses) to perform a particular calculation or relationship. Operands may come from a register file or may be indirectly accessed using the values of a register file.
In order to perform a set of operations that select from four or more operands (i.e., utilize four or more addresses), prior art calculation units must perform two or more instructions in more than one instruction cycle. It would be desirable to be able to utilize more than three addresses per instruction for computations that involve two operations and perform the above within only one instruction cycle. The present invention offers this advantageous function so that only one instruction cycle is consumed and two operations may be performed on the four addresses.
Specifically, in prior art calculation devices, instructions are executed in sequence to perform calculations. Often pointers are utilized in order to access the operands that are used in computations. When an operand used in a computation is indicated as a pointer, the syntax "*" is used before that pointer operand. Therefore, "*A" indicates that the value of operand A is actually an address that will point to a memory location where the desired operand is located. In this case the value A is a pointer to the operand. Once the computation involving this operand is complete, it is typically necessary to update the pointer so that another data operand can be accessed in a next or succedent operation. When operands are stored sequentially in a data file in memory, the pointers to these operands are updated or incremented upon each calculation. The below pair of instructions illustrate how a prior art system would perform the above functions: EQU C=*[A+P]+B EQU Increment P
The first instruction above involves four addresses. The value of operand B will be added to the value of an address pointed to by the value of A offset by the value of P. This result will be added to operand C. After, the value of P, the pointer, will be incremented so that [A+P] points to a new data value for computation. If the above instructions are executed again, the same value of B will be used and it will be added to a new value because the pointer "*[A+P]" was updated. This new result will be added to operand C. In order to perform the above, four addresses and two instruction cycles are required in prior art systems; one cycle for the computation and another cycle for the pointer update. What is desired is a system that would allow the pointer increment cycle to take place during the same instruction cycle as the computation cycle. This would reduce the overall processing time of the computer calculator to accomplish the above instructions. This would also offer some flexibility because the above sequence of steps is executed routinely in computer calculators. The present invention offers such parallel functionality with an instruction having four addresses.
Additionally, prior art computation units process operations on operands that are either in byte length (8 bits) or in word length (two bytes) but not a mixture of both without some performance loss. Therefore, the above operations will process one or two source operands that are either all in word length or all in type length. If there is a mixture of the two, the computation units of the prior art must perform a conversion between the operand lengths and this conversion forces the operation to execute outside of one computation cycle. What is desired is a processing or computation unit that allows a mixture of operand lengths within operands of one computation instruction while allowing the computation instruction to execute within one instruction cycle. The present invention allows such capability.
General purpose computer calculators and computation units are used by computer systems in order to perform pattern recognition for voice and handwriting recognition algorithms. These pattern recognition algorithms have particular calculations and calculation types that are executed in sequence in predetermined and repetitive manners. It would be desirable to be able to fashion a specially optimized arithmetic pipeline to process the steps required in a pattern recognition procedure. The present invention offers such capability.
Further, in systems that are developed for pattern recognition applications, specifically Dynamic Time Warping applications, computations are required to compute distance and best path values. Prior art systems for performing such computations involve one arithmetic pipeline. It would be advantageous to provide two specialized arithmetic pipelines, one optimized for DTW distance computations and the other optimized for DTW best path computations. The present invention offers such capability.
Accordingly, it is an object of the present invention to provide a single instruction format having both a register indexing mode function and an index update function that may occur within the same instruction cycle. It is an object of the present invention to be able to combine four addresses within a single computation instruction within an arithmetic pipeline device. It is further an object of the present invention to be able to process in parallel both a pointer update instruction as well as a computation instruction that utilizes the pointer value and is updated in parallel. It is also an object of the present invention to be able to execute an operation having operands of different lengths within one instruction cycle. It is yet another object of the present invention to provide the above functions in an arithmetic pipeline that is specially optimized for pattern recognition procedures to provide high speed pattern recognition capability. It is an object of the present invention to provide two arithmetic pipelines that operate in parallel for pattern recognition applications; one pipeline optimized for distance computations and the other pipeline optimized for best path computations. These and other objects of the present invention not specifically mentioned above will come in the discussions to follow.